2017-03-11 Board Review Notes
Participants
- Taiping Li
- Former user (Deleted)
- Kevin Chen (Unlicensed)
- Aleksa Bjelogrlic (Unlicensed)
- Minghao Ji
- Ryan Guile (Unlicensed)
- Calder Kitagawa
- Keith Wong (Deactivated)
- Karl Ding
Pre-Charge Controller
SR latch initialization
Output capacitor
2-inverter implementation
MUX output driving select line (MUX latch itself)
PMOS vs. NMOS -> Rdson losses
PCB
Move resistors away from edge
Thin out traces between resistors
Replace acute angles with T-junctions (i.e. 12V line on the right of the board)
Parts can be lined up better/silkscreen more clear
12V too close to pin 9 of U2
Thicken traces for HV section on bottom
Move traces away from edge
BMS_Interface
1mA biasing current (agree on biasing resistors)
Mode 3 for SPI
Source 150A current transducer
Isolation for BMS carrier board (common mode choke) -> safe rating of 200V
Moar LEDs
Low offset op amp
Telemetry
Schematic:
- BergStak pinout does not match Controller Board pinout
- Needs bulk capacitors
- Consider local 3V3 regulator instead of using Controller Board regulator - i.e. place power supply on board
PCB:
- C1, C2, C5, C6 are 0603 metric (0201 imperial), not 0603 imperial
- MicroSD should be at the edge of the board with the opening of the slot facing out - currently the MicroSD cannot be inserted
- Component placement of R1, R2, C3, C4 can be more organized to reduce vias and trace lengths
- Vias and trace lengths should be reduced in general
- 3V3 can be implemented using a polygon instead of daisy chained traces
- Try not to route traces in between pads if it is avoidable
For everyone:
Pull back ground plane from the edges!!!