In order to minimize the number of mistakes that could have been easily fixed before sending out a board, this page will hope to go through some common mistakes and other standards for our boards.
Make sure you clone a copy of this page under your project and run through this checklist before generating the gerbers. After going through the checklist, please attach your gerbers, BOM csv, and step file to the cloned page.
See https://jlcpcb.com/capabilities/Capabilities for more info.
JLC_DRC_Rules you can import, maintained by f39zhou
Schematic
- Appropriate template is used
- All elements are aligned to a 100mil grid
- GPIOs requiring ADCs are connected to ADC capable pins
- GPIOs requiring different interrupt controllers don't share the same pin number (e.g. PB1, PA1)
- Excessive current is not drawn from GPIOs
- Decoupling caps are present where needed
- Fuse followed by TVS is present at power input
Board - Traces
- High current loops have sufficient copper
- No acute angles between traces and traces, and traces and pads.
- Data lines have uninterrupted return paths
- Differential signals are tightly coupled and impedance controlled
- Teardrops are present
Board - Copper
- Ground planes are stitched together
- No ground islands or near-islands
Board - Mounting
- All mounting holes are kept away from the edge of the board
- There is adequate support for all the heavy components and connector plugs
- Make sure that edge mounting holes are about 2.7mm radius an are at least 3mm away from each edge. Lock these components after placement.
- Make sure there is a keepout/polygon cutout around mounting holes -> cannot be on the keepout layer → has to be copied on the bottom and top layers
Board - Connectors
- All power input connectors are 2-pin Molex Micro Fit (with the correct GND/PWR orientation)
- Unless higher current is required, under special circumstances
- Make sure there are enough GND test points!
- Headers and pins for all communication protocols - for now, 0.1" headers, to standardize on a debug connector
- I2C
- SPI
- etc
Board - Vias
- Vias are tented
- Unused via pads are removed, including on outer layers
- Planes are stitched
- Sufficient number of vias present for large currents
- Thermal vias present where appropriate
- Through holes have no paste opening
Board - Layers
- Make sure ONLY the board outline is drawn in the keep out layer
- Make sure all these layers are selected when generating your gerbers.
Silkscreen
- No overlapping text
- "JLCJLCJLCJLC" order number location is specified
- Connectors are labeled
- With function on top side (power input, CAN, Thermistor, etc.)
- With pinout on bottom side (or top side if possible)
- Logo is on the board
- Correct Name is listed
- Pin 1 labeled on all ICs
- Ensure bottom silkscreen is mirrored
- Optional parts (such as CAN termination) is labeled
- Ensure all polarized components are labelled
- Double-check all of silkscreen in 3D mode
BOM
- Ensure that all parts are in the BOM, and have Supplier part numbers - ideally manufacturer part numbers as well
- Ensure the no components are ordered on tape and reel
- This just increases cost for no reason (since we don't have a pick and place machine)
- Digikey part numbers that end in DKR usually have tape and reel - watch out for them!
- The BOM must be generated and all parts put on digikey to make sure everything is in stock
Generate Gerbers:
- How to export Altium PCB to gerber files (jlcpcb.com) ← follow this to generate gerbers
- NC Drill file is a txt file, make sure to include it in the zip
After Generating Gerbers
- Go to JLCPCB and upload the gerbers: https://jlcpcb.com/quote#/?orderType=1&stencilWidth=100&stencilLength=100&stencilCounts=5&stencilLayer=2&stencilPly=1.6&steelmeshSellingPriceRecordNum=A8256537-5522-491C-965C-646F5842AEC9&purchaseNumber=
- Make sure that JLC detects all layers and that the gerber viewer looks correct
- Upload the gerbers to the board sendouts page when available.
- Make sure the output files are in the GitHub branch and are well organized so that we can easily find the most recent rev
STEP File
- Make sure the STEP file is also generated, and in the correct location. Make sure whoever on Mech knows where the STEP file is so that enclosures, mounts can be designed for it.
- If having trouble opening the STEP file in Solidworks to verify that it is correct, see this thread: https://forum.solidworks.com/thread/223404