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See https://jlcpcb.com/capabilities/Capabilities for more info.Here are some DRC rules based on

JLC PCB's capabilities. View filenameJLC_DRC_Rules.zipheight250

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you can import, maintained by f39zhou

Appropriate template is used
All elements are aligned to a 100mil grid
GPIOs requiring ADCs are connected to ADC capable pins
GPIOs requiring different interrupt controllers don't share the same pin number (e.g. do not have PB1 and PA1 as separate inputs triggered by the interrupt controller)

Run DRC to verify spacing, make sure all traces are connected and find any net antenna. (All silk errors are not important as long as the silkscreen is thoroughly verified already for spacing).
Make sure to set the rules for trace widths to be relevant for the max and min for your board.
Check for any right angles in tracks
1. Does not make a difference in performance, but looks terrible
Check thickness of traces
Any high current traces should be sized appropriately
Go through the high current path through the board, around all components, etc. to make sure that there are no thin traces
Make sure there are absolutely no , PA1)
Excessive current is not drawn from GPIOs
Decoupling caps are present where needed
Fuse followed by TVS is present at power input

High current loops have sufficient copper
No acute angles between traces and traces, and traces and pads.
Ensure differential signals (CAN, isoSPI) run parallel and as close together as possible
Data lines have uninterrupted return paths
Differential signals are tightly coupled and impedance controlled
Teardrops are present

Keep the copper away from the very edge of the board
Copper to the edge or of the board can cause shorts along the side of the board
copper layer could peel up
increases the chance of corrosion on the exposed copper
Make sure there are no right angles in poly pours or solid regions - could act as antenna otherwise.
Ground planes are stitched together
No ground islands or near-islands

All mounting holes are kept away from the edge of the board
There is adequate support for all the heavy components and connector plugs
Large boards should have more than 4 mounting points
Make sure that edge mounting holes are about 2.7mm radius an are at least 3mm away from each edge. Lock these components after placement.
Make sure there is a keepout/polygon cutout around mounting holes -> cannot be on the keepout layer → has to be copied on the bottom and top layers

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All power input connectors are 2-pin Molex Micro Fit with part name "MSXV 2POS PWR" (with the correct GND/PWR orientation)
1. Unless higher current is required, under special circumstances
Easy attachment point for an oscilloscope probe GND - test points with the 'test point' part from digikey work well Make sure there are enough GND test points!
Headers and pins for all communication protocols - for now, 0.1" headers, to standardize on a debug connector
1. I2C
2. SPI
3. etc

For 2-layer boards, all vias >= 0.3mm hole, 0.6mm diameter
For 4-layer boards, all vias >= 0.2mm hole, 0.45mm diameter
1. Make sure vias do not interfere with internal layers (DRC should catch this)
Thermal vias should be small and numerous - we want the greatest surface area between planes as possible
For critical power traces, use multiple vias in parallel to reduce inductance and resistance
In general for vias, make the diameter 2x the size of the hole.
Vias are tented
Unused via pads are removed, including on outer layers
Planes are stitched
Sufficient number of vias present for large currents
Thermal vias present where appropriate
Through holes have no paste opening

All components are labeled in a logical manner
1. Maybe get someone else to look at it and make sure that they can follow the placement if any names had to be placed in weird orientations, etc.
No overlapping text
"JLCJLCJLCJLC" order number location is specified
Connectors are labeled
1. With function on top side (power input, CAN, Thermistor, etc.)
2. With pinout on bottom side (or top side if possible)
MSXIV Logo is on the board
Correct board Rev Name is listed
Pin 1 labeled on all ICs
Ensure bottom silkscreen is mirrored
Optional parts (such as CAN termination) is labeled
Ensure all polarized components are labelled
Double-check all of silkscreen in 3D mode

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