This is a page to keep track of our PCB revisions, document design changes, and receive feedback.
Revision 1
PCB design decisions
- All components on top of board except clik-mate connectors and debug LEDs (also TVS diode and 3 decoupling caps)
- Board dimension target is 5 cm x 5 cm (not of vital importance)
- Mounting holes (M4) on each corner
- Mezzanine connector will be close to the center of the board
- 2-Layer PCB with 1oz copper
Retrospective
- The board worked!
- Kevin's regulator design has not been tested yet, but Titus's regulator design worked well and had minimal ripple and relatively high efficiency under light loads (87% @ 10mA).
- The 1.25mm Clik-Mates were impossible to crimp and we'll definitely need a real crimper for the 1.50mm Clik-Mates that we plan on using.
- Most of our boards require powering the carrier board directly and the only purpose of the 12v rail is to power the regulator, so we can just remove the 12v connector from the controller board.
- The crystals are huge. They need to be replaced.
- The mounting holes are excessively large.
- The QFN chip is actually solderable by hand (Kevin Chen (Unlicensed))
- We definitely need a stencil to do proper reflow.
- The blue LEDs are way too bright.
- We haven't tested the crystals yet.
- We haven't the mezzanine yet.
Revision 2
Design Changes
- Remove extra regulator circuit (Kevin's), source smaller crystals, make all resistors and LEDs 0603
- Fix trace lengths for crystals
- Reverse voltage protection? Decided not to implement on controller as the 12V connector will be on carrier board
- Fix all footprints to match the Hardware Style Guide - Still in progress
- Replace board info silkscreen as directed in the Hardware Style Guide - Incomplete, will do for next rev
- Connector changes:
- Combine SWD and UART headers (we may be able to hack the programmers to also be UART to USB adapters) or replace them with prototyping headers - Used 6 pin SMT 0.1" header
- Replace 12V connector with test points - Decided not to use test points as the regulator has already been tested (decoupling caps can be used as test points)
- Replace mezzanine connector with 0.8mm pitch equivalent to increase lifespan and verify mating height - 0.5mm pitch connectors need to be tested first, then consider this if necessary
- Change all connector part numbers to vertical connectors
- put male side of mezzanine on controller board
- Add guide holes for mezzanine footprint
- Signal connectors switched to Duraclik
- Silkscreen pinout for connectors
- Reduce induced ripple on 12V rail - Test with different input caps
- Improve ripple behavior on 3.3V rail - Will test with different output caps
- Calibrate regulator to 3.3V (currently at 3.36V) - Shouldn't be a big issue
- Get stencils
- Lower blue LED brightness (spec an LED ), raise green LED brightness
Retrospective
- QFN is almost impossible to rework
- Need test points for everything, not just 1 for 3.3v - needed to scrape solder mask off to power the board
- Do silkscreen properly for diode, not have a tidy label in between pads
- Label as many things as we can with silkscreen
- We don't need to make everything as small as possible, it just needs to be reasonably sized.
- Consider larger resistances for LEDs, don't need them to be bright
- All components should have a 3D model for clearance
- Replace debug header with 0.05" Cortex-M standard
- CAN connectors should have the same pinout
- CAN has no direction so the silkscreen makes no sense
- MCU probably doesn't need every single alternate function, just things we'll actually use - the nets are probably a good level of verbosity.
- Lacks input protection → TVS, polyfuse etc.
- Probe the clock lines to check for performance
- Separate analog and digital grounds → performance has not yet been tested and will be hard to quantify without testing firmware
- Optimize regulator for better ripple performance
- 3V3 line has voltage ripple of about 60mV with 3mA draw from 12V upstream port (current was not measured at 3V3)
- 12mV of ripple is injected into the 12V lab supply line when 3V3 regulator is on
- More low ESR ceramic input caps of different values may reduce injected ripple into 12V line
- See evaluation module for ideas - seems to have 20mV ripple with reference design
- Current power approach
- Reduce noise so analog components can be run off of the controller board regulator - inspiration
- Use LDO fed from 3.3V rail for components requiring even less noise (unknown if necessary - none of our circuits should be that sensitive)
Revision 3
Retrospective
- Used reflow oven + stencils - turned out very well once we created a stencil jig with spare boards and tape!
- Stencil jig is essential - need to deposit the correct amount of solder paste, especially with
- Ripple is better, not as great as we hoped - ripple greatly reduces at loads > 100mA
- 89mV peak-to-peak variation at light loads vs. 29mV at 100mA in ADC testing - ELEC-
- LED brightness is good
- Might want to switch debug UART to USART3/4 - USART1/2 seem to have more features
Revision 4
Design Changes
- Remove some of the output filtering on the 3v3 regulator
- Add 3V LDO for analog components - shared ground should be fine
- Move test points a little farther away from the mezzanine?
Revision 5
Design Decisions
- Replaced EOL regulator with RECOM Power E-series DC-DC
- Replaced horizontal DuraCliks with vertical variants to allow for more flexibility in carrier boards
- Removed 32kHz crystal under the assumption that we would never use the RTC or CRS