how to use
before use: go to licenses and scroll down to PDN analyzer, right-click and click use
open a project’s schematic, then tools >> PDN analyzer
dc net identification
when the analyzer is initially opened, it will attempt to identify all dc power networks from the design’s net data based on common power network nomenclature
if not all potential power nets have been identified, deselect appropriate qualifiers filter options or see all nets and select enable all nets for filtering option
use the select check boxes and choose the power nets available to the analyzer. enter suitable voltage levels in the nominal voltage fields and click add selected
specify the power and ground nets
double click ‘power net’ and ‘ground net’ elements in the gui network graphic to open ‘choose net’ dialog. this offers the choice of power nets that have been identified
you can use the dialog’s qualifier/filter options to restrict or expand the listed nets
a source or load element can now be added between the power and ground networks (this is the same process for both load and source)
*you can hover the cursor over any element in the network to see additional informationright click in the network graphic space and select ‘add source’ / ‘add load’ to open device properties
to add a voltage source, select voltage source from the device type menu
the analyzer will attempt to choose the correct net connections - use the ‘Refdes’ menu to specify the component connection points of the source voltage (should be the component closest to the power/ground source depending on which you are setting)
the source parameters specify the attributes of the voltage source simulation
the max source current and pin current are left at the default settings
if the limits are set to specific current values, it will flag a violation of the simulation results exceed those values
to view the results
go to the analyzer’s visual tab and set the visual options to display ‘voltage’ for layers
the view of the selected path voltage drop is rendered with a colour gradient that corresponds to the voltage scale at the bottom of the view (red is max level and blue in minimum)
to display the current analysis, select the visual tab’s current density option
the colour levels in the board’s network path relate to the percentage of current density variation (red max calculated current density and blue minimum)
to view:
click 2d/3d in view section and go to the .PcbDoc tab of the board
to display and analyze power integrity results in the ground path, deselect the voltage/power network in the net list and select gnd network
to generate a report of the overall results, select report at the bottom and it will create a web link to the results
display and control options
you can clear the analysis results from the editor display which reverts to the graphics rendering to the standard board layout
the overlay option enables the board layout view - useful for confirming where a point of interest in the analysis is located
simulation settings
the analysis and degree of IR losses also depend on the specification of the board copper conductivity and Via wall thickness
right click and click settings to view and change these settings
metal conductivity
the base conductivity (or resistivity), temp coefficient and temp can be modified
pure copper – copper is typically assumed to have a conductivity of 5.88e7S/m at 25°C, and a conductivity thermal coefficient of 0.4%/°C
ex. this positive temp coefficient means raising the temp. compensation setting in the dialog from 25°C to 125°C will lower the simulation conductivity by 40%, to 3.53e7S/m
pcb copper – (default setting for simulations)
custom – choose this option enter specific conductivity or resistivity values for the simulation
via wall thickness
this is the weight of the via wall metal
can noticeably affect power network dc losses for thin walls. when of sufficient weight/size, it will not impede the dc performance of the design and shows the same current density as the power traces it connects
the simulation assumes the via diameter represents the finished hole size
finished hole diameter + (2 x wall thickness) = drill diameter
https://www.altium.com/documentation/altium-designer/pdn-analyzer-example-guidev2-ad
working with loads
you can add more loads as necessary
data probe
the probe tool allows the voltage or current density data at nominated points in the design to be recorded and comparedclick probe and click location to select the first location (the highest voltage point)
select difference to select the next location (the lowest voltage point)
