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- Planes are stitched together
- No ground islands or near-islands
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- Vias are tented
- Unused via pads are removed, except on outer layers
- Sufficient number of vias present for large currents
- Thermal vias present where appropriate
Board - Layers
- Only the board outline is drawn in the keep out layer
- Gerbers for the following layers are generated
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- No overlapping text
- Connectors are labeled
- With function on top side (power input, CAN, Thermistor, etc.)
- With pinout on bottom side (or top side if possible)
- Logo is on the board
- Correct Name is listed
- Pin 1 labeled on all ICs
- Ensure bottom silkscreen is mirrored
- Optional parts (such as CAN termination) is labeled
- Ensure all polarized components are labelled
- Double-check all of silkscreen in 3D mode
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