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- Appropriate template is used
- All elements are aligned to a 100mil grid
- GPIOs requiring ADCs are connected to ADC capable pins
- GPIOs requiring different interrupt controllers don't share the same pin number (e.g. PB1, PA1)
- Excessive current is not drawn from GPIOs
- Decoupling caps are present where needed
- Fuse followed by TVS is present at power input
Board - Traces
- High current loops have sufficient copper
- No acute angles between traces and traces, and traces and pads.
- Data lines have uninterrupted return paths
- Differential signals are tightly coupled and impedance controlled
- Teardrops are present
Board - Copper
- Planes are stitched together
- No ground islands or near-islands
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