In order to minimize the number of mistakes that could have been easily fixed before sending out a board, this page will hope to go through some common mistakes and other standards for our boards.
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Note: This checklist is not complete yet
Schematic
- Block Diagram to follow the function of the board and quickly understand
- Ensure that none of the GPIOs from the controller board have pins sharing the same number while requiring different interrupt controllers (e.g. do not have PB1 and PA1 as separate inputs triggered by the interrupt controller)
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- Run DRC to verify spacing, make sure all traces are connected and find any net antenna. (All silk errors are not important as long as the silkscreen is thoroughly verified already for spacing).
- Make sure to set the rules for trace widths to be relevant for the max and min for your board.
- Check for any right angles in tracks (does not make a difference in performance, but looks terrible)
- Check thickness of traces
- Any high current traces should be sized appropriately
- Go through the high current path through the board, around all components, etc. to make sure that there are no thin traces
- Make sure there are absolutely no acute angles between traces and traces, and traces and pads.
- Ensure differential signals (CAN, isoSPI) run parallel and as close together as possible
- Clearance for high voltage traces -- check DRC
Board - Design
- Polarized components point in the same direction.
- Test Points: If a TP is at risk of ripping off the board, consider not using the pad test point
- Signal Integrity
- Separate high-speed signals from low-speed signals
- Separate digital and analog signals as much as possible
- Minimizing crosstalk: When tracks need to cross, have them at right angles (on separate layers). This reduces the capacitance and mutual inductance between the lines
Board - Copper
- Keep the copper away from the very edge of the board
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- For 2-layer boards, all vias >= 0.3mm hole, 0.6mm diameter
- For 4-layer boards, all vias >= 0.2mm hole, 0.45mm diameter
- Make sure vias do not interfere with internal layers (DRC should catch this)
- Thermal vias should be small and numerous - we want the greatest surface area between planes as possible
- For critical power traces, use multiple vias in parallel to reduce inductance and resistance
- In general for vias, make the diameter 2x the size of the hole.
- No blind/buried vias (JLC PCB does not support them)
- Add via stitching
Why + source
Board - Layers
- Make sure there is a keep out layer surrounding your board.
- Make sure all these layers are selected when generating your gerbers.
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- All components are labeled in a logical manner
- Text-rotation: Make sure that text could be read from one of two orientations/rotations
- Maybe get someone else to look at it and make sure that they can follow the placement if any names had to be placed in weird orientations, etc.
- Connectors are labeled
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- MSXIV Logo is on the board
Here are some places you can get the logo from:
Board: | Dimensions:
Board: | Dimensions:
Board: | Dimensions:
- Correct board Rev is listed
- Pin 1 labeled on all ICs
- Ensure bottom silkscreen is mirrored
- Optional parts (such as CAN termination) is labeled
- Ensure all polarized components are labelled
- Double-check all of silkscreen in 3D mode
- LEDs should be labelled and named appropriately
- Test Points should be named appropriately
BOM
Configuring Your BOM in Altium Designer
- Ensure that all parts are in the BOM, and have Supplier part numbers - ideally manufacturer part numbers as well
- Ensure the no components are ordered on tape and reel
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If having trouble opening the STEP file in Solidworks to verify that it is correct, see this thread: https://forum.solidworks.com/thread/223404
more new things to add: