Signal Integrity Analyzer

when should the analysis be performed?

“Traditionally, signal integrity tools are designed to work with a fully routed board. While this gives accurate results because each individual trace length is known, it does mean that the analysis is performed quite late in the design cycle.”

Signal Integrity Analyzer

• before you start, make sure the schematic/pcb document is part of the project (crosstalk analysis cannot be performed)

for a pcb document, you can also run si from any of the schematic documents (reflection and crosstalk analysis can be performed)

1. before using:

1. make sure there is at least 1 ic with an output pin attached to the net you are simulating

2. associated si model type for each component has to be correct

3. must be supply nets design rules (generally at least two rules [power and ground])

4. a signal stimulus design rule may be set up

5. layer stack for pcb must be set up correctly. thickness of all layers, cores and prepreg must be set up correctly

   1. go to design >> layer stack manager to set up layer stack

2. signal integrity design rules in schematic

• pcb specific design rules for si can be defined in the schematic if added as parameters

• for si, add a pcb rule to identify the supply nets and their voltage

  • to add the supply net

    1. place >> directives >> pcb layout

    2. press tab to display parameters dialog

    3. select the undefined rule and click edit

    4. click edit rule values to display the choose design rule type dialog

    5. click supply nets, ok

    6. enter the voltage for the supply net

    7. place the pcb rule directive on the appropriate net (a dot will appear when the directive is properly attached)

    8. create another pcb rule directive for gnd net and other supply nets

    • * in schematic editor, the scope of the rule is defined where the parameter is added. in pcb editor, the scope of the rule is defined within the rule itself

• signal stimulus design rule

  • when the rule is run, the stimulus is injected at each output pin on the net being analyzed

  • you need to create a sheet parameter for this rule since this requires a design rule with a scope of all

    1. design >> document options and click on parameters tab in the document options to add a sheet parameter

    2. click on add as rule and edit rule values to display choose design rule type

    3. select signal stimulus, click ok

    choose stimulus kind, start level and times

• si parameters such as overshoot, undershoot, impedance and signal scope requirements can be specified

  • these rules can be configured and enabled as tests and the panel will graphically display which nets failed which tests

  • design >> rules (can also set up these rules using parameters in schematic editor and will appear in pcb rules and constraint editor dialog)

3. model assignments:
https://www.altium.com/documentation/altium-designer/a-look-at-creating-library-components-ad

1. this is required for every component on the pcb for this analyzer to work. if one does not work go the next option

   1. manufacturer – this is a good place to look since this is the website for the manufacturer that makes this device. typically, there will be a link to any available model from the page dealing with the specific device supplied in SPICE or PSpice format

   2. altium designer’s SPICE model wizard – use this to create and automatically link a SPICE3f5 device model to an existing or new library component. if linking to a new component, the component will be created automatically by the wizard. supported types are semiconductor capacitor, semiconductor resistor, current-controlled switch, voltage-controlled switch, JFET lossy transmission line, uniform distributed rc transmission line, diode, and BJT

   3. third-party modeling tools – various simulation software packages contain features for modeling a device

   4. dedicated modeling companies – you may be able to source the required model from a third-party company which creates simulation models based on a spec

   5. by hand – the model can be created by yourself and will require good knowledge of the language in which the model definition is being written.
      **WILL LINK TO SEPARATE MODEL ASSIGNMENTS PAGE

2. compatible forms on altium
   for a simple model, needs to be saved with mdl extension (.mdl). for complex SPICE subcircuit, must be saved with ckt extension (.ckt)

   1. SPICE3f5

   2. XSpice

   3. PSpice

4. how to use:

1. go to tools > signal integrity

   1. you can now have some or none of the schematic components in the pcb, but any places should be linked with component links (project > component links)

   2. if you do not have si models attached to every component, you will need to set up model assignments using the Model Assignments dialog
      about model assignments

      1. select the component to modify the model

      2. signal integrity has 7 types of components - resistor, capacitor, inductor, diode, BJT, connector and IC

      3. if the component is an IC, the technology type will determine the characteristics of the pin models used in the simulation

      4. check the “update schematic“ column in the setup signal integrity dialog for components that are to be updated and update the models

      5. to add an si model to a placed component, open the component’s properties by double-clicking, click the add button and select signal integrity as model type

      6. it is usually sufficient to enter a type and value for parts such as resistors and capacitors, and technology type for ics
         about ibis files

      7. to use an ibis file (to specify the ic model’s input and output characteristics), click on the import ibis in signal integrity model dialog

      8. select the component and import the pin models from the ibis file
         editing pin models

      9. it is possible to add or edit an existing pin model - also available for other types such as BJTs, connectors and diodes

      10. click the add/edit model button in the signal integrity model dialog if this button is available for the type

2. then the si setup options dialog displays the first time you run this command on an open project

   1. set the track impedance and average track length (only required for unrouted nets or there are nets not transferred to a pcb)

   2. click analyze design to run initial default screening analysis

      • * four default tolerance rules and any si rule are enabled and run for the first time and can be set later in si panel - menu >> set tolerances

      si set up options in schematic mode only

   3. if no pcb, you can change the si setup options in the si panel at any time

   4. track setup allows configuration of the default length of tracks when simulating

   5. click supply nets and stimulus tabs to display and enable net and stimulus rule info (allow another interface for defining these characteristics)

3. after the initial setup, the si panel will be loaded with data from the screening analysis

   1. the initial screening analysis provides a fast simulation to get more information and identify critical nets for closer examination (detailed reflection and/or crosstalk)

   2. there are 3 categories: passed, failed, not analyzed

      1. passed - all values inside bounds defined by tests

      2. failed - at least one value outside tolerance values

      3. not analyzed - not screened for some reason (right-click/click menu, select show/hide columns and enable analysis errors to view reason)

5. reasons for failed nets

• containing a connector, diode or transistor and no output pins or multiple output pins

  • when nets contain bi-directional pins and no dedicated output pin in the net, each pin is simulated separately

  • the worst-case result is displayed

**it is possible for nets to have other errors that lead to incorrect analysis in both screenings and further simulations - highlighted in bright red

**nets that have been simulated (not routed on pcb) are light gray

6. checking failed or not analyzed nets

• if nets are highlighted bright red

  1. select a net, right-click, and select show errors

  2. view all information for a net - right-click and select details

7. performing analysis on individual nets

• nets must be selected on the right hand list of the signal integrity panel
  1. double click on the net in the left hand list to select it and move to the right
  2. in the selected state, you can perform further configurations before running a simulation

8. set the direction of bidirectional pins in a net

1. select the affected net in the right hand list

2. change the in/out status for each selected bidirectional pin by right-clicking and selecting a status

9. running analyses

1. click reflections or crosstalk button in the si panel to generate waveforms

https://techdocs.altium.com/display/ASIAE/Performing+Signal+Integrity+Analyses