Schematic
- Block Diagram to follow the function of the board and quickly understand
Board - Traces
- Run DRC to verify spacing, make sure all traces are connected and find any net antenna. (All silk errors are not important as long as the silkscreen is thoroughly verified already for spacing).
- Make sure to set the rules for trace widths to be relevant for the max and min for your board.
- Check for any right angles in tracks
Does not make a difference in performance, but looks terrible
- Check thickness of traces
- Any high current traces should be sized appropriately
- Go through the high current path through the board, around all components, etc. to make sure that there are no thin traces
- Make sure there are absolutely no acute angles between traces and traces, and traces and pads.
- Ensure differential signals (CAN, isoSPI) run parallel and as close together as possible
Board - Copper
- Keep the copper away from the very edge of the board
- Copper to the edge or of the board can cause shorts along the side of the board
- copper layer could peel up
- Increases the chance of corrosion on the exposed copper
- Make sure there are no right angles in poly pours or solid regions - could act as antenna otherwise.
Board - Mounting
- All mounting holes are kept away from the edge of the board
- There is adequate support for all the heavy components and connector plugs
- Large boards should have more than 4 mounting points
- Make sure that edge mounting holes are about 2.7mm radius an are at least 3mm away from each edge. Lock these components after placement
Board - Connectors
- All power input connectors are 2-pin Molex Micro Fit (with the correct GND/PWR orientation)
Unless higher current is required, under special circumstances
- Easy attachment point for an oscilloscope probe GND - test points with the ‘test point’ part from digikey work well
- Make sure there are enough GND test points!
- Headers and pins for all communication protocols - for now, 0.1" headers, to standardize on a debug connector
I2C
SPI
etc
Board - Vias
- For 2-layer boards, all vias >= 0.3mm hole, 0.6mm diameter
- For 4-layer boards, all vias >= 0.2mm hole, 0.45mm diameter
- Make sure vias do not interfere with internal layers (DRC should catch this)
- Thermal vias should be small and numerous - we want the greatest surface area between planes as possible
- For critical power traces, use multiple vias in parallel to reduce inductance and resistance
- In general for vias, make the diameter 2x the size of the hole.
Board - Layers
- Make sure there is a keep out layer surrounding your board.
- Make sure all these layers are selected when generating your gerbers.
Silkscreen
- All components are labeled in a logical manner
- Connectors are labelled
- MSXIV Logo is on the board
- Correct board Rev is listed
- Pin 1 labeled on all ICs
- Ensure bottom silkscreen is mirrored
- Optional parts (such as CAN termination) is labeled
- Ensure all polarized components are labelled
- Double-check all of silkscreen in 3D mode
BOM
- Ensure that all parts are in the BOM, and have Supplier part numbers - ideally manufacturer part numbers as well
- Ensure the no components are ordered on tape and reel
- The BOM must be generated and all parts put on digikey to make sure everything is in stock
After Generating Gerbers
- Go to JLCPCB and upload the gerbers: https://jlcpcb.com/quote#/?orderType=1&stencilWidth=100&stencilLength=100&stencilCounts=5&stencilLayer=2&stencilPly=1.6&steelmeshSellingPriceRecordNum=A8256537-5522-491C-965C-646F5842AEC9&purchaseNumber=
- Make sure that JLC detects all layers and that the gerber viewer looks correct
- Upload the gerbers to the board sendouts page when available.
- Make sure the output files are in the GitHub branch and are well organized so that we can easily find the most recent rev
STEP File
- Make sure the STEP file is also generated, and in the correct location. Make sure whoever on Mech knows where the STEP file is so that enclosures, mounts can be designed for it.