These ICs work together in an active clamp flyback converter topology:

InnoSwitch4-CZ

ClampZero

I think this one is good for our application:

https://www.digikey.ca/en/products/detail/power-integrations/INN4077C-H182-TL/16967692
(Updated to support max current capability of 3.4A Peak)

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Block diagram from InnoSwitch4

Lots of design examples are provided in the ‘design examples’ of the InnoSwitch page:

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The DCM mode of operation will be used in order to decrease the size of the transformer. An example can be found here:

Microsoft Word - DER-930 180W 20V9A 90-265VAC Battery Charger INN4177C-H189 CPZ1076M PFS5177F (power.com)

DER-979 - 100 W In-Wall USB Outlet with Selectable Output Voltage

DER-979 - 100 W In-Wall USB Outlet with Selectable Output Voltage Using InnoSwitch4-CZ PowiGaN and ClampZero

DER-943 - 60 W General Purpose/Notebook PC Power Supply

DER-943 - 60 W General Purpose/Notebook PC Power Supply using InnoSwitch4-CZ and ClampZero

Uses: INN4075C and CPZ1075M

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Notes from reading:

Primary-side

• C10 bypass capacitor, picked based on value of desired current limit of InnoSwitch

• C5 is the main clamp capacitor, w Zener to protect

  • in CCM, takes care of leakage inductance, in DCM also takes care of magnetizing energy

• When FluxLink signal from secondary receieved, HSD is sent to turn on Clamp switch

  • R2 configures the delay for ZVS turn off for the ClampZero fet

• R5 & R6 allow for voltage sensing (but why 2 in series if both just go to pin…?

• BPP is the bootstrap pin that powers the ClampZero IC

  • on startup, powered by internal high voltage current source which charges C10

  • C7 & C8 provide local decoupling, R1 prevents over current in BP2 line

• During normal operation, coils 2&3 on the transformer provide power for the IC

  • Rectified w D2 and filtered with C9 to provide constant voltage to BPP

• Frequency and I_Lim are selected based on output load

• If BPP current too high (above I_SD), chip restarts

Secondary-side:

• C12 & C13 are the ‘main capacitors’ for filtering the output

  • C16 reduces high frequency ripple

• RCD snubber in R8/C11/D4 reduces high frequency ringing + EMI

• Synchronous Rectifying FET Q1 and D3 are the rectifiers

• voltage sensed by FW through R7 determines when to turn Q1 on

  • for CCM, fet turns off before the next cycle via signal from ClampZero

  • for DCM, fet turns off once the voltage across is is below V_SR(TH)

• For CV, output voltage is sensed in FB by voltage division across R9 and R10

  • internal reference voltage of 1.265 V

• Current sensing is through R14, measured by the IS pin

  • threshold voltage of ~35mV

Transformer Design

• Bias winding to supply at least 4mA of current to BP1 and BP2 pins

Efficiency

We will spec our parts to have 100% load at ~60W, so nominal load of 30W is 50% load

• according to this, we can expect to achieve that ~94% efficiency

InnoSwitch4-CZ-Datasheet Studying

https://www.power.com/sites/default/files/documents/InnoSwitch4-CZ-Data-Sheet.pdf

INN407x is constant voltage output, INN417x is constant current output

• We want INN407x for constant voltage

ZVS of CalmpZero Switch

For CCM, t_LLDL, the delay time between ClampZero turn off and Innoswitch conductionis determined by placing a resistor between HSD and SOURCE pin:

“centering this delay and the lowest point of the Drain voltage is critical for optimizing ZVS”

• t_LLDL is a function of fet drain node capacitance and leakage inductance of transformer

For DCM, t_HLDL is a function of fet capacitance and leakage + magnetizing inductance of transformer

If constant current regulation is not required, the ISENSE pin must be tied to SECONDARY GROUND pin

Component Selection

Clamp Capacitor

Ilim Capacitor

Resistor for HSD to ZVS Delay Programming

OV Protection Zener Voltage

Schematic Doodling