FET Testing

Protected +12V

It was noted that at higher currents, there appears to be a rather large voltage drop between the input and output of the board. At the maximum designed current of 5A on the Protected +12V rail, the back to back P-Channel MOSFETs controlled by the PowerPath IC heated up significantly. The following table was tested with the E-Load set at CC = 5.0A, and a 30A ATC Automotive Fuse in the fuse holder. 

With this in mind, either 2 FETs should be put in parallel with each other, or an alternative FET should be found to handle the current. Ideally something with a smaller Rds(On) would be helpful in reducing the voltage drop. 

This Vishay SI7997DP appears to be a pin compatible replacement that offers significantly higher power dissipation and current draw. This will be tested at a later date. 

Unprotected +12V

Since the unprotected +12V rail does not go through the P-Channel MOSFET, losses are only incurred from the connector, vias, and N-Channel MOSFETs near the connectors. The following table was produced by connecting Q5 to the E-Load, and using a 30A ATC Automotive Fuse in the fuse holder. With these numbers, it can be seen that the average resistance between the fuse and the output is approximately 63 miliohms. 

Another test was done with the two parallel N-Channel MOSFETs designed for the horn and lights. It can be seen that with 2 FETs in parallel, the voltage drop is significantly less at higher currents. The average resistance between the fuse and the output is approximately 48 miliohms.