Power Path FETs Power Dissipation and Temp Rise
- Micah Black
During testing, we measured the drive voltage of the FETs (Vgs) to be 4.013V. We will use this figure to calculate resistance and temperature rise.
FET datasheet for reference:
The first step is to define a few operating conditions as boundaries for our analysis.
Parameter | Max Value | Notes |
|---|---|---|
Ambient Temp | 60C | Automotive |
Current | 17A | DC-DC maximum value |
Continuous | 10A | Estimated maximum |
Thermal Resistance | 50 C/W | For 1” copper PCB for each FET (2” total for back to back FETs). Paralleled fets will be assumed to fit on the same board area |
Rds on | 6.3 mOhm x 1.3 = 8.2 mOhm | Vgs = 4V, Tj = 90. Datasheet figures 11 & 12. |
Calculated Values
Max power dissipation | (90-60) / 50 | 0.6W (per FET) |
Max Rds On (1 fet) | 6 mOhm | Using 10A Continuous |
Max Rds On (2 fets) | 12mOhm | 10A, assuming 50/50% current sharing |
Max Rds On (2 fets) | 8.6 mOhm | 10A, assuming 70/30% worst case current sharing |
Max Rds On (3 fets) | 15 mOhm | 10A, assuming 40/30/30% current sharing |
So we should be fine with 2 FETs on each input (power supply, DC-DC, AUX).
So including relevant safety factors (extremely high ambient temp, high continuous current, highly uneven current sharing) 2 parallel groups of back to back FETs should be completely fine.
A note on board space - we can squish them together and add a heatsink on them to make the board smaller (for future revs once we are sure that it works and have tested thoroughly).
It would be a good idea to add thermistors near the FET on the board if testing proves that they heat up under high load. This was apparently discussed for MSXII: Power Distribution Revisions