Page Comparison

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•  For 2-layer boards, all vias >= 0.3mm hole, 0.6mm diameter
•  For 4-layer boards, all vias >= 0.2mm hole, 0.45mm diameter
  1. Make sure vias do not interfere with internal layers (DRC should catch this)
•  Thermal vias should be small and numerous - we want the greatest surface area between planes as possible
•  For critical power traces, use multiple vias in parallel to reduce inductance and resistance
•  In general for vias, make the diameter 2x the size of the hole.

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•   Go to JLCPCB and upload the gerbers: https://jlcpcb.com/quote#/?orderType=1&stencilWidth=100&stencilLength=100&stencilCounts=5&stencilLayer=2&stencilPly=1.6&steelmeshSellingPriceRecordNum=A8256537-5522-491C-965C-646F5842AEC9&purchaseNumber=
•  Make sure that JLC detects all layers and that the gerber viewer looks correct
•  Upload the gerbers to the board sendouts page when available.
•  Make sure the output files are in the GitHub branch and are well organized so that we can easily find the most recent rev

STEP File

•  Make sure the STEP file is also generated, and in the correct location. Make sure whoever on Mech knows where the STEP file is so that enclosures, mounts can be designed for it.
  1. If having trouble opening the STEP file in Solidworks to verify that it is correct, see this thread: https://forum.solidworks.com/thread/223404

SENDOUT MATERIAL:

https://www.digikey.ca/short/23294ffq
(SMBJ33CA-TR available on Mouser)