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  1. Flash ADC: Also known as a parallel ADC. It compares the input voltage to a set of reference voltages, the output is a binary code. They are called flash ADCs because they convert instantly. Below is an example of a 2-bit flash ADC.

    image-20240830-061047.png

  2. Successive Approximation ADC (STM32 usually uses this): Binary search algorithm to approximate the input voltage. It starts with the MSB defined by the resolution and compares the analog input and the maximum value (through a DAC).

    For example, a 3-bit SAR sampling 4.5V will approximate the binary output ‘100’. This is 4V, so the comparator shows that the input > approximate, so the MSB must be 1. It then moves on to the next digit and approximates ‘110’, which is 6V. Since input < approximate, the bit remains 0. You notice that the final output will be 4V. A SAR is significantly limited by its resolution.

    image-20240830-062742.png

  3. Sigma-Delta ADC: Uses oversampling and noise-shaping techniques for high accuracy and resolution. Samples at a very high frequency, and then filter out the noise. It then quantizes the samples and outputs a value. These are typically slower than the above ADCs but offer very high precision. Sigma-Delta ADCs are incredibly complex, if you’re interested in learning more take a look at this resource: https://www.analog.com/en/resources/technical-articles/sigmadelta-adcs-tutorial.html

  4. Dual Slope ADC: Integrating ADC that measures input voltage by comparing it to a reference voltage during fixed time intervals. Input voltage is integrated over another distinct time interval.

    • Integration Phase: The input voltage (V_in) is integrated over a fixed period (T_int), which results in a voltage ramp. The slope of the ramp is proportional to the input voltage.

    • De-integration Phase: After the integration period, a reference voltage (V_ref, usually of opposite polarity) is applied. The time it takes for the ramp to return to zero is measured (T_deint).

    • Measurement: The time measured during the de-integration phase is proportional to the input voltage by a factor of V_ref / T_int.

This ADC is effective since noise is processed out by integration. You can see this in the below visualization:

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https://www.asdlib.org/onlineArticles/elabware/Scheeline_ADC/ADC_ADC_Dual_Slope.html

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