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Updates

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July 9, 2020

There were a few bugs to work out in the code to print the values, but they didn’t match what was expected. I probed the COMM lines between the 2 chips, and there was nothing - just held to 5V for 2s (beofore the chip goes to sleep) with the pullup resistor. (pins 17,18,19)
I also probed the output of the chip - pulled to GND for the whole time. (pin 43)

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I (Micah Black will hard-code some more stuff while Gerald Aryeetey (Deactivated) looks in to a fix for this.

Updates

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July 10, 2020

We fixed the PEC and the correct order for the COMM register data bits.

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Next steps I’ll try getting some wires soldered to the TQFP mux package and hopefully connect them to the logic analyzer or scope so we can see what is actually happening (I had verified communication was present measuring just 1 channel at a time, so I am unsure if timings are accurate.

Updates July 11, 2020

I hooked up the LTC external SPI interface (the one to the MUX) to the logic analyzer and verified that the signal is getting passed along correctly.

This screenshot should be correctly setting the bits A2 and A0 to enable the input 5 of the mux.

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None of this makes sense…
So going back through the configuration and reading everything carefully:

ADG731: Data is shifted in to the register, MSB first, on the FALLING edge of the clock.
Checking this against the logic analyzer output, it was set up to sample on the RISING edge of the clock (CPHA=1). Swapping this to the correct CPHA=0 for sampling on the falling edge:
(This is the same spot in the transmission as the above diagram)

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Notice that all the bits are shifted by 1, and the there is a ‘1' that gets shifted in to the first nEN bit of the ADG731’s input shift register. Thus, the mux is NEVER ENABLED. I think we found our problem.

Time to dig through the LTC6811 datasheet and see if the external SPI mode can be changed.
And I think we have a bigger problem than we realized here. The LTC6811 only supports SPI MODE 3:

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Which is in conflict with what the ADG731 supports - either:

• CPOL=1, CPHA=0 for SPI MODE 2

• CPOL=0, CPHA=1 for SPI MODE 1

So at this point, we need to find a way to modify the interface, or we need to find a new MUX.

Options:

AGD732 - The ADG732 is a parallel controlled 32ch mux. Pins A0-A5 control the channel, and the WR pin must be toggled in order to latch the input data. This means that we need 6 pins to control it, and thus the device is not compatible.

Modify Interface - The LTC6811 outputs are Open-Drain, and the inputs on the ADG731 I believe are high impedance. If we invert the clock signal, I think we will be able to get sampling in the correct spot of the signal. SCLK is on pin 19 of the ADG731, and pin 33 of the LTC6811. The signal is pulled HIGH to 5V0 with R1.

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I think I can cut the trace between PIN 19 and R1 and insert an N-FET and an extra pull-up resistor to achieve the signal inversion.

This is the circuit that would be put in between the pins to invert the clock:

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I swapped in that circuit between the pins, using a DMN3023L for the external FET since there were some lying around from BMS carrier (these are the FETs used to power the contactors). Turns out the FETs are likely a little too powerful and/or the pullup resistance isn’t strong enough since the signal never recovers. The scope shot below is of the LTC GPIO pin acting as SCLK. You can see it properly disables the FET, but it takes 10+uS to fully recover to disable the FET. This time is a function of the gate capacitance of the FET and the external pullup resistance.

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Also visible in this graph is a cool effect that I’ve heard of before but never observed - The Miller Effect.

Basically, it is a plateau in the gate voltage as the FET turns on. This happens because the internal capacitors inside the FET are charging up, but also because these capacitors change in value as the FET turns on. At the start of the curve, the voltage starts rising in a waveform that would be expected from a simple RC circuit. It rises like this until the FET starts to turn on. When the FET starts to turn on, there are extra charge carriers that start flowing through the Drain to Source path. The presence of these extra charge carriers increase the parasitic Gate to Drain capacitance, thus slowing down the rate of voltage rise - giving the plateau observed in the FET switching waveforms.
More info on the Miller Effect as well as FET behaviour is in these Application Notes (which I think are an amazing read) (Vgp - Voltage Gate Plateau - in the figure is the Miller Plateau)

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So, we know a power FET is not the right part for the job - a small signal FET or BJT should work much better. I have some 2n3904 NPN BJTs lying around which I think will do a bit of a better job.

I swapped in the 2N3904 BJT and I got some data!!!!

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And its very accurate!

Here’s the SCLK signal with the 2N3904 signal:
You can see it rises up to just under 5V between pulses, which is well above the 2.4V logic high threshold of the ADG731:

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YAY! It all works.

This is the circuit to implement the clock inversion:

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Here's a picture of the test setup with the modifications:

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And for good measure, here’s a picture of the logic analyzer output with the modificiations:

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James Jo We need to implement this circuit on AFE rev 2.

Now we just have to figure out why we are only getting 6 readings from the LTC6811 IC.

Gerald Aryeetey (Deactivated) This is our next task.