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  • MOSFETs 
    • N-channel vs P-channel
    • Parallel MOSFETs
  • Power resistors vs normal resistors

                     

Fig 2. Pre-Charge HV - power resistors                   Fig 3. Pre-Charge Logic - comparator

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  • Op-amps and op-amp comparators
  • Negative feedback and positive feedback


             

     Fig 3. Pre-Charge Logic - AND gate                 Fig 4. Pre-Charge Logic - SR Latch

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An SR latch (the IC in figure 4) is placed after the AND gate in order to latch the output of the AND gate. So long as the enable (ENA) pin is powered (which it always is in accordance with ISO_12V), the latch works like a normal SR latch with S4 and R4 corresponding to set and reset for the output Q4. When S4 receives a logic high, Q4 will be connected to Vdd, gaining a logic high as well. A capacitor is placed between the reset pin and its source to keep the reset input low for a short amount of time. 

Things to research:

  • Fundamental gates (AND, OR, NOT, etc.)
  • SR Latches (go to datasheet for logic diagram and truth table)

Image Added Image Added

        Fig 5. Pre-Charge Logic - Optoisolator and MC Contact Driver                                     Fig 6. Motor Interface Pcb - Optoisolator (U5)

The first IC on the left of figure 5 is an optoisolator (or optocoupler) used to interface between the HV and LV sides of the board. You can see this in figure 6, the optoisolator spans across a gap where the HV side (top) is isolated from the LV side (bottom).