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For higher current applications, many standard vias offer more current carrying capacity per area than one very large via. Controlled impedance signals at or above USB High Speed (480Mbps) shall have controlled impedance vias. Saturn toolkit can be used to calculate via impedance and current carrying capacity. Standard JLC plating thickness is 18um, and the expected temperature rise shall be no more than 25C.
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Through hole test points shall be un-tented PTH with a 0.7mm hole and at least a 1mm pad diameter.
Location
SMD test points are required for power rails and any analog voltages being measured by an ADC. Both SMD test points and 2.54mm headers are required for digital communication busses.
Thermal Relief
Thermals should be present unless there is sufficient reason to remove them. Some reasons to remove thermals include high current paths in a switcher, or when a thermal cuts down significantly on the area of a polygon. Generally decoupling caps should have thermals.
Logo
The top layer silkscreen shall contain the following graphic, with text under the “Midnight” letters in the following format:
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