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For higher current applications, typically multiple many standard size vias offer greater layout flexibility more current carrying capacity per area than one very large via. Controlled impedance signals shall have controlled impedance vias. Saturn toolkit can be used to calculate via impedance and current carrying capacity. Standard JLC plating thickness is 18um, and the expected temperature rise shall be no more than 25C.
Stitching Vias
Comprised of standard vias placed on an offset 5mm grid, with 1mm clearance to pads/traces/board edge. Sometimes they can be more dense due to smaller board size or specific requirements.
Test Points
Size
SMD test points shall have an exposed copper area of at least a square with edge length of 1.27mm.
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