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Now since the opto-isolator we are using inverts the logic, it makes sense to use a NAND gate instead. This way, output from the opto-isolator will be the same as Fig. 3. above, and can then be latched with the SR Latch. 

Changes for Rev2

•  Fix diode silkscreen on the bottom of the board

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•  Remove R1, replace R2 with a smaller value for more current into comparator

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•  Q1 should have 1/2/4/6 and 4 swapped 

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•  Ultra-fit and Dura-Clik connectors instead of Clik-Mates

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•  Add passthrough for relay sense line (shorted when relay is closed, open circuit when relay is open)

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•  Fix voltage drop with MOSFET stages

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•  Add hysteresis to avoid bouncing 

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•  Add an NAND gate between negative input and comparator output

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•  Try to increase voltage going into opto-isolator. Around 2V right now due to voltage division

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•  Consider using non-tented vias or through hole test points. Some TPs were ripped off

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• •  Also don't put TPs directly on a trace as if it falls off it takes the entire trace with it 

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