These ICs work together in an active clamp flyback converter topology:
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C12 & C13 are the ‘main capacitors’ for filtering the output
C16 reduces high frequency ripple
RCD snubber in R8/C11/D4 reduces high frequency ringing + EMI
Synchronous Rectifying FET Q1 and D3 are the rectifiers
voltage sensed by FW through R7 determines when to turn Q1 on
for CCM, fet turns off before the next cycle via signal from ClampZero
for DCM, fet turns off once the voltage across is is below VSR(TH)
For CV, output voltage is sensed in FB by voltage division across R9 and R10
internal reference voltage of 1.265 V
Current sensing is through R14, mesaured measured by the IS pin
threshold voltage of ~35mV
Transformer Design
Bias winding to supply at least 4mA of current to BP1 and BP2 pins
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Efficiency
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We will spec our parts to have 100% load at ~60W, so nominal load of 30W is 50% load
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For DCM, tHLDLis a function of fet capacitance and leakage + magnetizing inductance of transformer
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If constant current regulation is not required, the ISENSE pin must be tied to SECONDARY GROUND pin
Component Selection
Clamp Capacitor
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Resistor for HSD to ZVS Delay Programming
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OV Protection Zener Voltage
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Schematic Doodling (WIP)
