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The rated current shall be at least double the expected application. The maximum current is typically defined by the thermal limit of how much heat the part can handle due to IR losses. Note that especially for high current FETs, the max current is given for specific conditions, often at a case (surface) temperature (Tc) of 25C. In reality, it is not realistic to keep the surface of the part at 25C under full load, as this would require sub ambient cooling. Thus, appropriate component derating must be performed.
Schematic
Style
Grid
All schematics shall be drawn exclusively on a 100 mil grid for neatness. I will be sad if you use a 50 mil grid.
Decoupling
IC decoupling shall be achieved by a minimum of one 0.1uF MLCC capacitor per power pin. Additional decoupling shall be added if warranted by the application, such as in high power devices. The datasheet will generally have recommended decoupling schemes. It is acceptable to round decoupling cap values to nicer numbers, ie 0.47uF to 1uF. Be weary of excessive capacitance resulting in inrush current.
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