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The rated current shall be at least double the expected application. The maximum current is typically defined by the thermal limit of how much heat the part can handle due to IR losses. Note that especially for high current FETs, the max current is given for specific conditions, often at a case (surface) temperature (Tc) of 25C. In reality, it is not realistic to keep the surface of the part at 25C under full load, as this would require sub ambient cooling. Thus, appropriate component derating must be performed.
PCB
Mounting
The M2.5 hex standoff component shall be used to PCB mounting homes. The hole shall be 2.7mm in diameter, with a keep-out area 6mm in diameter.
Trace Width
Standard signals shall use 50ohm traces with an impedance profile set in Altium. Use Saturn Toolkit to calculate required width for higher current applications.
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Standard vias are generally 0.5/0.3mm pad/hole. For higher current applications, typically multiple standard size vias offer greater layout flexibility than one very large via. Controlled impedance signals shall have controlled impedance vias. Saturn toolkit can be used to calculate via impedance and current carrying capacity. Standard JLC plating thickness is 18um, and the expected temperature rise shall be no more than 25C.
Test Points
Size
SMD test points shall have an exposed copper area of at least a square with edge length of 1.27mm.
Through hole test points shall be un-tented PTH with a 0.7mm hole and at least a 1mm pad diameter
SMD test points are required for power rails and any analog voltages being measured by an ADC. Both SMD test points and 2.54mm headers are required for digital communication busses.
Logo
The top layer silkscreen shall contain the following graphic, with the board name and revision in smaller next under the “Midnight” letters.
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