We have tasks that process events one at a time to completion. They can place tasks/events on each other queues synchronously.
...
peripherals can all get their own tasks with shared memory to control tasks
Control tasks are acting like FSMs and each has their own event queue
They can write back to their event queue
Other tasks can also write tasks to other event queues
NOTE: All critical processing happens in a “critical task” with a high priority that will prempt everything else
° CAN will happen at regular intervals with acceptable latency
Jarvis:
Inforce scheduling on every task for limited runtime
for SPI and I2C same thing as RX and TX, the information can be sent and received but the actual task can send and receive
More OOP for task design such that there are
constructors (i.e. init)
destructors for a cleanup
Abstraction for inheritance from a common parent class
Shared Memory: One struct with every info/pointer in it.
Abstraction and inheritance for tasks accessing the shared memory
self clean up for each task