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This is the circuit that would be put in between the pins to invert the clock:
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I swapped in that circuit between the pins, using a DMN3023L for the external FET since there were some lying around from BMS carrier (these are the FETs used to power the contactors). Turns out the FETs are likely a little too powerful and/or the pullup resistance isn’t strong enough since the signal never recovers. The scope shot below is of the LTC GPIO pin acting as SCLK. You can see it properly disables the FET, but it takes 10+uS to fully recover to disable the FET. This time is a function of the gate capacitance of the FET and the external pullup resistance.
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Also visible in this graph is a cool effect that I’ve heard of before but never observed - The Miller Effect.
Basically, it is a plateau in the gate voltage as the FET turns on. This happens because the internal capacitors inside the FET are charging up, but also because these capacitors change in value as the FET turns on. At the start of the curve, the voltage starts rising in a waveform that would be expected from a simple RC circuit. It rises like this until the FET starts to turn on. When the FET starts to turn on, there are extra charge carriers that start flowing through the Drain to Source path. The presence of these extra charge carriers increase the parasitic Gate to Drain capacitance, thus slowing down the rate of voltage rise - giving the plateau observed in the FET switching waveforms.
More info on the Miller Effect as well as FET behaviour is in these Application Notes (which I think are an amazing read) (Vgp - Voltage Gate Plateau - in the figure is the Miller Plateau)
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So, we know a power FET is not the right part for the job - a small signal FET or BJT should work much better. I have some 2n3904 NPN BJTs lying around which I think will do a bit of a better job.
I swapped in the 2N3904 BJT and I got some data!!!!
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Thermistor on Cell # | Expected mV | Reading mV | Error mV (Expected - Reading) |
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0 | 1500 | 1502.8 | +2.8 |
1 | 744.36 | 742.8 | -1.56 |
2 | 1500 | 1501.3 | +1.3 |
3 | 959.186 | 958.7 | -0.486 |
4 | 1500 | 1504.5 | +4.5 |
5 | 1013.245 | 1013.2 | -0.045 |
And its very accurate!
Here’s the SCLK signal with the 2N3904 signal:
You can see it rises up to just under 5V between pulses, which is well above the 2.4V logic high threshold of the ADG731:
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YAY! It all works.
This is the circuit to implement the clock inversion:
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Now we just have to figure out why we are only getting 6 readings from the LTC6811 IC.