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If we turn on a second input with a lower priority also at the edge of its voltage range, then the board behaves similarly, except this time with both inputs switching between valid and invalid:
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So we have seen failure modes when the inputs are at the edge of their voltage range, but this does not seem to explain why discharging the capacitors would change anything. Let’s try and figure that out.
Testing continued by removing 1 of the capacitors after the FETs to bring the capacitance down to 100uF total. This seemed to do the trick, but is this amount of capacitance required? With only 1 capacitor on the board, I could not get it to trigger the reset loop condition.
Letting the capacitors discharge seems to be a counter-intuitive way to get the inrush current low enough that the effects of resistance do not cause a substantial voltage drop - you would think that discharging more would give a larger inrush current - so I went searching in the datasheet for soft-start since I seem to remember seeing that somewhere
From the Datasheet, pg 10:
“The LTC4417 gate driver pulls down on G1, G2 and G3 with a strong P-channel source follower and a 2µA current source. When the clamp voltage is reached, the P-channel source follower is back biased, leaving the 2µA current source to hold G1, G2 and G3 at the clamp voltage. To minimize inrush current at start-up, the gate driver soft-starts the first input supply to connect VOUT, at a rate of around 5V/ms terminating when any channel disconnects or 32ms has elapsed. Once slew rate control has terminated, the gate driver quickly turns on and off external back-to-back P-channel MOSFETs as needed. A SHDN low to high transition or VOUT drooping below 0.7V reactivates soft-start.”
So yes - we need to drain the capacitors to below 0.7V in order to reactivate soft-start. One solution would be to just turn on a load to drain them quickly (but the controller board will only be able to activate the load for so long, but a better solution would be a discharge resistor on the board. We will need to make sure that the caps can be fully discharged within a given amount of time in order to properly activate the soft start.
FET slew rate limiting should not be required in this situation, as all of our supplies can handle high transient loads, and this will reduce the switchover time.
The other way to implement this would be to control the shutdown pin. If all 3 of the supplies are not valid (e.g. pulled to 3V3), and the chip is still powered, then we can pull the shutdown pin high in order to restart the chip completely and go through the soft start cycle again. With this solution we can add larger capacitors to the board, and should not have any issues with switchover times as the capacitor can store the required energy to hold up during switchover.