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Testing continued by removing 1 of the capacitors after the FETs to bring the capacitance down to 100uF total. This seemed to do the trick, but is this amount of capacitance required? With only 1 capacitor on the board, I could not get it to trigger the reset loop condition (at least with the range of switching speed I had by pushing the output on/off button).
I also verified the 256mS period for re-validating a channel.
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This trace (below) for the input voltage seems like it could trigger an undervoltage and then an overvoltage fault immediately after, but since the setup was a little janky, I would not trust that this is an actual observed spike instead of an artefact of the measurement setup.
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Solutions to Discuss
Letting the capacitors discharge seems to be a counter-intuitive way to get the inrush current low enough that the effects of resistance do not cause a substantial voltage drop - you would think that discharging more would give a larger inrush current - so I went searching in the datasheet for soft-start since I seem to remember seeing that somewhere
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The other way to implement this would be to control the shutdown pin. If all 3 of the supplies are not valid (e.g. pulled to 3V3), and the chip is still powered, then we can pull the shutdown pin high in order to restart the chip completely and go through the soft start cycle again. With this solution we can add larger capacitors to the board, and should not have any issues with switchover times as the capacitor can store the required energy to hold up during switchover. We should make sure that on initial startup this does not keep the chip in shutdown.