The precharge circuit runs entirely based on hardware (i.e. no firmware is required).
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Things to research:
- MOSFETs
- Enhancement vs depletion
- N-channel vs P-channel
- Parallel MOSFETs
- Power resistors vs normal resistors
- Inrush current
Fig 2. Pre-Charge HV Sch- power resistors Fig 3. Pre-Charge Logic Sch - comparator
Fig 1 The goal is to connect the battery to the motor controllers when the motor controller capacitor reaches at least 95% of the battery voltage. This is done using voltage dividers and a comparator. Fig 2 shows the power resistors used to limit the current when pre-charging with two voltage dividers connected to either side. The voltage dividers connected to the left and right sides of the power resistors are used to compare the voltage of the battery and motor controllers and . On the battery side, the voltage divider is set to reduce the 150V from the HV line 150V to 9.39V while on the battery side and 9.84V on the motor controller side. Basically, if motor controller side, the voltage divider is set to reduce 142.5V (95% of 150V) to 9.35V. If the pre-charge circuit is on, IN- will be 9.34V, and IN+ will rise from 0V to 9.84V. Aside , thus IN+ will be greater than IN- when the motor controller capacitor passes 142.5V. Aside from lowering the voltage, the resistances used in the voltage dividers are set such that when the motor controller reaches 95% of the voltage on the battery side, IN+ will be greater than IN-.
Fig 2 3 shows an op-amp comparator taking in IN+ and IN- as its non-inverting and inverting inputs respectively. This comparison will output a logic high when IN+ is greater than IN-, effectively signaling that the motor controller has reached 95% of the battery's voltage and pre-charge is complete. The op-amp is set with a positive feedback loop to prevent the comparator output from bouncing oscillating between logic high and logic low which may happen when the circuit is transitioning from a logic high to a logic low. The positive feedback latches the output to a logic high and makes it so there must be a significant difference between IN+ and IN- to switch the output.
Things to research
- Voltage division
- Op-amps and op-amp comparators
- Negative feedback and positive feedback
Fig 34. Pre-Charge Logic Sch - AND gate Fig 4 Fig 5. Pre-Charge Logic Sch - SR Latch
Using only the comparator shown above presents another problem whereby the comparator may output a logic high when the op-amp is powered but its inputs aren't, such as when the battery relay to the pre-charge circuit is open. The AND gate solves this by taking in the comparator's input as well as a reading from IN+ , or from the motor controller side of the pre-charge circuit. The MOSFET directly connected to the IN+ on the bottom circuit of Fig 4 is an N-channel enhancement MOSFET (normally open). This acts as a switch that only closes when a gate voltage is supplied by IN+. This MOSFET is initially open, which allows the 12V source directly above to apply a positive voltage on the gate of the next MOSFET, a P-channel. The P-channel MOSFET (normally closed) then acts as an initially open switch due to the gate voltage supplied by ISO_12V_SW. The 12V source directly above the P-channel MOSFET is thus disconnected from the AND gate. When IN+ applies a positive voltage to the N-channel MOSFET, the 12V source above is connected to ground and the P-channel MOSFET closes due to the loss of its gate voltage. Consequently, the 12V source ISO_12V_SW above the P-channel is connected to the AND gate. This way, the AND gate will only output a logic high if the comparator signals pre-charging is finished, and the motor controller is indeed charged. The MOSFETs act as a resistive switch converting the IN+ reading to something that matches the comparator's logic high.
An SR latch (the IC in figure 4) is placed after the AND gate in order to latch the output of the AND gate. This means that so long as the AND gate supplies a logic high signal once to the SR latch, the latch will continue to output a logic high even if the AND gate stops supplying the logic high. So long as the enable (ENA) pin is powered (which it always is in accordance with ISO_12V), the latch works like a normal SR latch with S4 and R4 corresponding to set and reset for the output Q4. When S4 receives a logic high, Q4 will be connected to Vdd, gaining a logic high as well. A capacitor is placed between the reset pin and its source to keep the reset input low for a short amount of time. . The reset pin R4 is initially supplied a voltage setting the initial latch state to be reset (Q4 = 0). Then R4 is set to a logic low. While pre-charging, both inputs S4 and R4 are set to logic low, which latches the previous state (initially reset). When S4 is supplied a logic high from the AND gate, the inputs are now S4 = 1, R4 = 0, which changes the latch to be in the set state (Q4 = 1). Q4 will now remain high and continuously supply the Vdd voltage regardless of the AND gate.
Things to research:
- Fundamental gates (AND, OR, NOT, etc.)
- SR Latches (go to the datasheet for logic diagram and truth table)
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The first IC on the left of figure 5 is an optoisolator (or optocoupler) used to interface between the HV and LV sides of the board. You can see this in figure 6, the optoisolator spans across a gap where the HV side (top) is isolated from the LV side (bottom). Following the latch previously mentioned, when ISO_LATCH_OUT outputs a logic high, the MOSFET is closed connecting the cathode (CAT) pin to ground. This connects the circuit from the anode (AN) completing the circuit and powering the GaAsP LED inside the IC. When this happens, the Vo will output a logic high and close the MOSFET to the contactor driver. This signals the relay connecting HV directly to the motor controllers to close.
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